Shahzad Raza

Experience

• 

  National Radio Telecom Corporation of Pakistan

  Aug 2017 - now

  Designed the state machines of waveform modules like upsampling, group delay removal & burst division at different sampling rates.Designed a state machine for generic clock divider using sequential & combinational logic to generate clock i.e multiple of 9.6kHz.Designed Root Raised Cosine (RRC) filter of BPSK modulation for inter symbol interfacing and pulse shaping for waveform development.Designed the FIFO state machine and debouncing logic for clock domain crossing of different modules.Developoed an algorithm in Vitis HLS of fractional-PLL for VCOout(MHz) & DAC transfer function for analog output voltages in Vitis HLS.Designed Instruction set architecture in verilog for controlling the RF chain of V/UHF SDR using zynq 7010.RTL Implementation of custom SPI protocol for transmitting/receiving multistream data from master device at 25MHz clock rate.Designed the arrays in VHDL for storing the analog voltage values against frequency of Power Amplifier in 1,2,5 & 10Watt configuration for each waveform.Designed a switching matrix in verilog for each waveform configuration of RF chain.Designed a controller for hopping the PLL's using ping pong method & RF chain switching of upto 1250hops/sec.Designed the linear search algorithm in VHDL to find the target voltage against preset channel in fixed frequency and hopping mode.Designed a state machine to tune the harmonic filter using frequency look-up table using I/O standard (LVCMOS33) logic.Porting Firmware in EMMC on customized zynq-7020 boardRTL development,simulation by writing test benches and on chip debugging using ILA.Customized IP drivers development using userspace I/O framework.Secure boot implementation on ZYNQ 7000 series. Show less Hands-on experience on ADI ADRV9361 System on Module(SOM) SDR, Zynq SoC and Virtex.Responsible for designing and implementation of Signal processing in VHDL and Verilog.Design & Implemented real-time sweep generator IP with sampling rate of 61.44MHz, BPSK and QPSK waveforms with 40MHz real-time bandwidth using VHDL targeting various Software Defined Radio (SDR) hardware like ad9361.Hands-on experience of interfacing Texas Instruments (TI) ADC(ADS4249) and DAC(DAC34H84) on FMC with zedboard using LVDS protocol.Designed and implemented waveforms and DSP algorithms like (frequency detection, local maxima and minima, clock domain crossing, DDS, FIR, CORDIC, FFT) using VHDL or Verilog targeting various Software Defined Radio (SDR) hardware like ad9361.RTL Implementation of customized one wire protocol for antenna tuning.Worked on PS-PL communication using AXI standards and AXI DMA.Responsible for Embedded Linux development, kernel and driver customization based on customized FPGA Show less

  • Senior FPGA Engineer

    Nov 2021 - now

  • FPGA Design Engineer

    Aug 2018 - Nov 2021

  • Trainee Engineer

    Aug 2017 - Aug 2018