Chieh-Jen K.

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Hillsboro, Oregon, United States

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Timeline
About me
Advanced CMOS process integration technologist and manager
Education
- Rutgers, The State University of New Jersey-New Brunswick
  2006 - 2012
  PhD Electrical and Computer Engineering
- National Cheng Kung University
  1997 - 2001
  Bachelor of Science (B.S.) Engineering 75/100
- National Tsing Hua University
  2001 - 2003
  Master of Science (MS) Material Science and Engineering 85/100
Experience
- TSMC
  Jul 2003 - Jul 2006
  Process Engineer for 0.25/0.22/0.18/0.15/0.14 um CMOS BEOLPVD/CVD/CMP processing development and improvementPVD: AlCu, Ti, TiN , Co salicide, Ti salicideCVD: W-CVD for contact layer CMP: STI-CMP, ILD-CMP, W-CMPRTP: RTA, RTO in-line defect reduction, yield improvement and failure analysis of BEOL Process Engineer for 0.25/0.22/0.18/0.15/0.14 um CMOS BEOLPVD/CVD/CMP processing development and improvementPVD: AlCu, Ti, TiN , Co salicide, Ti salicideCVD: W-CVD for contact layerCMP: STI-CMP, ILD-CMP, W-CMPRTP: RTA, RTOin-line defect reduction, yield improvement and failure analysis of BEOL
  - Senior Process Engineer
    Dec 2004 - Jul 2006
  - Thin Film Process Engineer
    Jul 2003 - Dec 2004
- Rutgers University
  Sept 2006 - Mar 2013
  PhD ECE department
  1.Design, fabrication and reliability issues of ZnO based TFTs 2.Novel Sensor platform based on ZnO TFTs (biosensor and UV photodetector) 3.ZnO high voltage TFTs for DC-DC converter of system on glass (SOG) application4.ZnO based resistive switching devices (RRAM) for reconfigurable electronics and optoelectronics
- Intel Corporation
  May 2013 - Jan 2019
  Technology lead for INTEL 16nm FEOL process integration.Design rule and DFM definition for FinFET transistor technology.FinFET and GAA transistor technology 22nm/14nm FEOL process integration development, yield-performance co-optimization, yield analysis, device performance enhancementRD to HVM technology transfer
  - PTD Staff lead process integration engineer
    May 2017 - Jan 2019
  - PTD Senior FEOL Integration engineer
    May 2013 - Apr 2017
- Intel Corporation
  Apr 2019 - Jan 2021
  PTD Senior Staff TD manager
  Lead team of process integration, device and yield analysis engineer to enable new embedded memory technology.Lead pathfinding effort for BEOL transistor technology exploration and successfully integrated it with CMOS advanced FINFET process architectureDefine technology roadmap and milestone of next generation embedded memory technology for client computing products.
- TSMC
  Jan 2021 - Aug 2022
  FEOL process integration senior manager
  FEOL process integration department manager supervising process integration, device engineering and yield analysis sections for N5/N4P/N3 technology.Develop BKM process knobs for transistor performance enhancement.NTO and NPI operation DLY/PLY improvement, wafer level and product level reliability enhancementExcursion prevention, cost reduction , process capability improvement
- Apple
  Aug 2022 - Nov 2022
  Senior Quality Engineer
  Senior Quality Engineer for Apple SOC product portfolio ( A series-SOC, M-series SOC and PMIC)Mac-book and iPhone custom silicon quality engineering activities
Licenses & Certifications
- Semiconductor Manufacture Training Courses, 320 Hours
  Industrial Development Bureau, Ministry of Economic Affairs, Taiwan
- VLSI processing and Semiconductor Manufacture Technology
  National Nano Device Laboratory, Hsinchu, Taiwan
Honors & Awards
- Awarded to Chieh-Jen K.
  Finalist, Qualcomm Innovation Fellowship Qualcomm Apr 2012 Reconfigurable Wireless Multi-mode Biosensor arrays
- Awarded to Chieh-Jen K.
  TSMC IDL Award TSMC Dec 2004 Overall Productivity and Quality Improvement of AlCu Sputtering Tools
- Awarded to Chieh-Jen K.
  TSMC Outstanding Engieering Contribution Award TSMC Dec 2004 Overall Productivity and Quality Improvement of AlCu Sputtering Tools