William LIN

Experience

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  Advantech

  Aug 2007 - Mar 2012

  Senior hardware engineer

  1. Support EMI member to test EMI Class A certification on ODM-CPCI9002 for CISPR22(information product)2. Maxing load with Cable and without Cable configuration.3. Create BOM and upload to BENQ webpage Maintain system for BOM maintenance.4. Second source part verification for Burning test over 24 hours.5. INTEL Platform Romley Platform Sandy Bridge chipset Sequence measurement and check spec meet or not.6. LAN Chip I210/I350 chipset Schematic drawing build up and Layout checklist review.7. Drawing schematic and Layout check for LSI SAS2008 HBA Raid 8. Function validation for SAS 0/1/5/10 (PCIE GEN2) and LAN Throughput test.9. Support to DQA team to check signal quality issue.10. Prepare Shipping list for system to PM on DVT stage.11. Support Thermal team to build up APM9600 system Burning test on High Humid/ High Temperature /Low Humid / Low Temperature and these means four corner test in chamber.12. Support Intel X 86 hardware for ODM customer’s request. (Major customer Crossbeam). Show less

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  Supermicro

  Apr 2012 - Jun 2015

  Senior Hardware Design Engineer

  1. Troubleshooting Mass Production issue on LDO AP1084 thermal more over heating issue and it cause “random” operation on 5% failure rate in high temperature.2. Configuring Product quick start guide and user manual review on X9SAE/X10SLA/X10DRL-CT series.3. RMA failure issue analytics, Hardware issue escalation initiatives with Vendor.4. Monitoring Factory sample running for test plan, FW working instruction and Hardware verification instruction.5. Configuring PCH / CPLD GPIO setting for Input / output H & L & OD table.6. Handling the X9SAE/X10SAL/X10DRL-CT schematic and Layout placement and routing plan.7. Following up ISO9001 certification processes and document control for review and reply question.8. Setup length assessment and ask Vendor to provide connector/ IC simulation IBIS-AMI model preparation (Switch worse case length for SI simulation.)9. Integrate members EE EVT function test items and Crystal Calibration test report from vendor.10. Release stress tools SOP and instruction guide for Function to verify. 11. Measurement on the PCB impedance for Time-Domain Reflector(TDR) EX: Single End 50/40ohm & Differential 85 ohm/100ohm12. Support quality Assistant member to debug signal quality and bug issue free, my previous project 13. X10DRL-CT is got the good of compute performance, density, thermal management and power 14. efficiency to lower their overall total cost of ownership and some comments from tweak town. Refer to web link: http://www.tweaktown.com/reviews/7127/supermicro-x10drl-ct-intel-c612-server-motherboard-review/index.html Show less

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  Wistron

  Jun 2015 - Feb 2020

  Associate Technical Director

  1. Project review and must strictly require cost (EX: key parts bom / PCB material) upon optimization routing path and expect to meet best performance and reliability. 2. Offer suggestions and review the detail Storage redundant Key feature in current design project upon customer demand. 3. Review the project leader with Function team’s test plan (Signals Verification team / Qualification team), in order to meet commission of System feature for 1U/2U/4U in INTEL Platform Grantley/Purley Application.4. Release system topology routing plan and review system total solution cable list in 1U/2U/4U system and Key part BOMs and Board placement re-confirm.5. Review team member‘s co-work with Philippines layout member for optimization of the optimization routing path.6. Review Project leader and three to four team members work loading status and collect process flow by weekly meeting. 7. Implement solving the issue in deadline (RFQ) and meet customer goals.8. Familiar skill for Allegro Design Entry CIS and Allegro Physical Viewer to review for other team members.9. Share trouble-shooting experience in Layout routing location and bottleneck for complex system.10. Review and modify team member’s system Administration for System Level BOM / System Rear IO / System Front IO port design (USB/COM/VGA/10G RJ45…etc).11. Patent “Point to point automatically detect application for systems)” approve by Wistron Patent Engineer12. Review cost saving of the Venus Storage system BOM cost for all SKUs phase and at least 10~15 dollars cost saving for common bom replacement in 2U system.13. Dispatch members for weekly update within the EA test progress and Function team issue clarification Show less

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  HP

  Feb 2020 - now

  Design Engineer

  - Workstation development of INTEL RKL-S platform discussion with cross function team and ODMs difficulties topic.- Review PCA Qualification Process and Checklist for risk can be reward.- Responsible for leading ODM a technical portfolio spanning in Workstation product.- Strong confident to make a risk build after evaluating cross function suggestion within Spec.- Create Risk assessment for new feature application interface and how difficulty with difference of previous WKS20 project. Show less