Jagadish Nayak

Experience

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  AMD

  Aug 1992 - Aug 1996

  Senior Design Engineer

  Senior Design Engineer: - Designed one pipeline stage (ALIGN2) of twelve stage super-scalar RISC x86 processorProduct Development Engineer: - Defined and developed methodology for global timing management for synthesis - Wrote micro-code for Am486 microprocessor instructions

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  Metaflow Technologies

  Sept 1996 - Feb 1999

  Senior Verification Engineer

  Verification leader of the Cache sub-system and Bus Interface Unit (CSSBIU) block (2 million transistors) for Pentium-II class, super-scalar, speculative, out-of-order execution RISC microprocessor

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  Los Angeles Times

  Jun 2000 - Aug 2000

  Intern

  Marketing and Strategy Internship (while in MBA program)

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  AdaptiveInfo

  Jan 2001 - Jun 2001

  Intern

  Marketing and Strategy (part-time while in MBA program)

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  Trimedia

  Aug 2002 - Mar 2003

  Member of Technical Staff

  Verification of the Audio In/Audio Out module in a dual-processor multimedia SOC

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  Sun Microsystems

  Mar 2003 - Apr 2010

  Principal Engineer

  Senior Verification Engineer: - Developed and designed assertion (OVA) methodology for multi-threaded SPARC processor - Evaluated and developed methodology for using assertions to run formal verification - Presented papers on assertion and formal verification experience at internal Sun conference attended by design and verification groups (150+ engineers) - Full chip gate level verification for 3 tape-outs of multi-threaded, multi-core processor. - Verification for the Data Switch Unit (cross-bar switch) and Performance Monitor Unit: - Created and implemented test-plan - Assertions in OVA to be used both in dynamic simulation and formal verification environments - Code coverage Show less

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  Broadcom

  May 2010 - Dec 2017

  Principal Engineer

  Verification Lead: - Developed and implemented test plan to verify Synopsys based processor ARC sub system- Emulation of Advanced Stream Processor (ASP) for hardware and firmware verification on Xilinx based design - Designed and implemented test plan for verification of three third-party Security IP blocks incorporated in SoCProject Management: Core lead for 5 cores delivered by my division for System-on-Chip

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  Cycuity

  Sept 2018 - Dec 2023

  Senior Security Applications Engineer

  - Pre-Sales presentations of Information tracking security product - Tutorial presentations at Exhibition and Conferences - Training on using security product at customers - Proof of Concept Evaluations at customer sites; assist customers in creating security requirements, running security product on their designs, debugging requirement violations and suggesting hardware fixes. - Collaborate with internal R&D Team to enhance tool and feature set based on customer input; Test and verify new enhancements internally as well as at Customer sites. - Extensive experience with Defense and Commercial Customers Show less

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  Cycuity

  Feb 2024 - now

  Senior Principal Security Applications Engineer

  - Asset based Security Threat Analysis- Security Requirement Creation- Analysis of Information Flow from Secure Assets- Collaboration with Customers and internal R&D to improve and enhance Radix Security Product