Saurabh Rai

Experience

• 

  PinE Training Academy of VLSI & Embedded

  Jul 2018 - Aug 2021

  - Full Custom Layout- Static Timing Analysis- Digital Design- Tanner S-edit & L-edit tool- Analog Design- Unix Friendly (all basic & advanced commands)- Bash Scripting - Learning Verilog and testing it on XILINX ISE Tool. => Structural Modeling. => Behavioral Modeling. => Gate Level Modelling. => Data Flow Modelling.- Learning VHDL and testing it on XILINX ISE Tool. => Structural Modeling. => Dataflow Modeling. -Work on Schematic Design on FPGA board on XILINX ISE Tool.- Worked on Implementation of Signed CALCULATOR Schematic on FPGA Board (SPARTAN 6).- Worked on Implementation of 4-way Traffic Light Controller Schematic on FPGA Board (SPARTAN 6).- Worked on Testing/Verification of Different Types of Combinationals and Sequentials Schematic Desgins on FPGA Board.

  • Trainee in ASIC & Full Custom Layout

    Aug 2020 - Aug 2021

  • Trainee

    Aug 2019 - Aug 2020

  • Trainee

    Jul 2018 - Jul 2019
• 

  ACL Digital

  Aug 2021 - Apr 2023

  Worked as Memory Layout Engineer for Synopsys as a Client.Worked on Custom Compiler.Worked on SRAM.Worked on Different tech nodes like icf18a, SS8, SMIC 14nm.

  • Layout Design Engineer

    Feb 2022 - Apr 2023

  • Intern

    Aug 2021 - Jan 2022
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  Texas Instruments

  Apr 2023 - now

  Analog Layout Engineer

  Working as a Analog Layout Engineer