Amar Ridhwan

Amar Ridhwan

Process Engineer (FOL- Wafer Sort)

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location of Amar RidhwanIpoh, Perak, Malaysia

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  • Timeline

  • About me

    Assistant Engineer (EOL- Final Test)

  • Education

    • University Malaysia Perlis (UniMAP)

      2012 - 2014
      Bachelor's Degree in Engineering (Electrical/Electronic) INDUSTRIAL ELECTRONIC ENGINEERING 2.81
    • Tuanku Sultanah Bahiyah Polytechnic, Kulim Hi-Tech Park, 09000 Kulim, Kedah

      2009 - 2011
      Diploma in Engineering (Electrical/Electronic) Electronic engineering 3.33
  • Experience

    • Inari Technology Sdn Bhd

      Feb 2014 - Oct 2016
      Process Engineer (FOL- Wafer Sort)

      -Involve and cover for Wafer Sort process by using sawing DISCO model DFD641/651/6341 & DAD3350/641, Acceretech AD2000T, laser mark (CSM2000) and back grinding machine (DFG8540).-Generate work instructions and provide relevant training for operators/ trainers and supervisor.-Successfully setup machine and conversion based on customer requirement.-Analyze, optimize and standardize the parameter all Sawing machine model DFD641/651/6341, DAD3350/641, and AD2000T.-Collecting process data for evaluation, improvement, optimization and analysis activities by using SPC, FMEA, Six Sigma and DOE-Doing the engineering rework from sawing, back grind and laser mark process means broken, overcut, under grind, offset marking, incomplete saw and undercut wafer.-Responsible to settling line issue and do eval quality improvement, yield, cost and cycle time from beginning until the end of the process at wafer sort department.-To dispose production LYT lots, on hold lots on daily basic and trigger to superior & production manager.-Follow up with special engineering builds (from customer) and ensure it is meeting their requirement.-Experiance in preparing 8D report.Achievement- Improve overall yield from 95% until 99% for dicing faults & chipping issue for sawing m/c.- Reduce contamination after saw issue from 70% until 30%, optimization washing parameter.- Reduce broken wafer issue from 65% until 15%, improve WI & workout with training department.- Improve production output and quality from 200 wafer per-shift until 350 wafer per-shift after optimization sawing parameter.- Reduce sawing quality issue from 75% until 10% after optimization sawing parameter.- Help to reduce cycle time from 3.5 day to 0.8 day for engineering lot disposition.- Reduce reject quality for full saw device from 1000 and above until below 500 for backside chipping & hairline crack issue Show less

    • Carsem

      Nov 2016 - now
      Assistant Engineer (EOL- Final Test)

      -Cover enggineering scop for final test department (Eagle test system)-Successfully setup handler Delta adge, Hontech, JHT, Chroma 3180, Multitest99/93, SRM, Pentamaster, Symtax and conversion based on production planning.-Analyze troubleshooting reject and follow up with customer for integrated or non integrated device issue:-Low yield-SBL fail -High Cont-Eqa valid-On hold-Doing verification and resolve the problem on Eagle tester and hardware for Device unable to pass.-Doing verification onhold lot as customer request.-Follow up with customer for lot disposition. -Suport Engineer for evaluation Socket Pin and collecting data.-Follow up with special engineering builds request from customer and ensure it is meeting their requirement.-Suport demand on urgent product shipment and cooperate with production; maintenant; and Qa to resolve technical issue.-More on hands on skill. Show less

  • Licenses & Certifications

    • AutoCAD 2014