Giuseppe Di Guglielmo

Giuseppe Di Guglielmo

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  • Timeline

  • About me

    Experienced System-level Designer, High-Level Synthesis Adept and Verification Engineer

  • Education

    • Università degli Studi di Verona

      2006 - 2009
      Ph.D. Computer Science
    • Università degli Studi di Verona

      1999 - 2005
      Laurea Magistralis Computer Science
  • Experience

    • Università degli Studi di Verona

      Jan 2006 - Feb 2010
      • Postdoctoral Fellow

        Apr 2009 - Feb 2010
      • PhD Student

        Jan 2006 - Apr 2009
    • Tallinn University of Technology

      Oct 2006 - Feb 2007
      Visiting Student
    • Certess (SpringSoft - Synopsys)

      Aug 2007 - Dec 2007
      Intern
    • Purdue University

      Sept 2009 - Feb 2010
      Visiting researcher
    • 東京大学

      Mar 2010 - Apr 2011
      Visiting Research Fellow
    • Università degli Studi di Verona

      May 2011 - Oct 2012
      Postdoctoral Fellow
    • Columbia University

      Nov 2012 - May 2022
      • Associate Research Scientist

        Oct 2013 - May 2022
      • Postdoctoral Research Scientist

        Nov 2012 - Oct 2013
    • Fermilab

      Jul 2022 - now
      Senior ASIC Engineer
    • Electrical & Computer Engineering | Northwestern University

      Dec 2022 - now
      Adjunct Associate Professor
  • Licenses & Certifications

    • Machine Learning by Stanford University (Prof. Andrew Ng)

      Coursera
      Feb 2017
      View certificate certificate