Yash Patel

Experience

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  Dharmsinh Desai University

  Dec 2021 - May 2022

  RTL design Intern

  • Executed the development of Verilog-based SPI and APB protocols during an internship, crafting robust testbench to examine protocol drivers for hardware interfaces, ensuring seamless functionality and performance optimization.• Implemented SPI with master and two slaves in FPGA, utilizing Verilog in Quartus, featuring a finite state machine approach for interfacing with multiple protocols like I2C, executing full duplex mode, different clock phase and polarity modes, variable character lengths, and MSB/LSB data transmission, while optimizing power consumption via clock gating for a 20% energy reduction and enhanced efficiency.• Implemented APB slaves in Verilog, conducted testbench and verification with SystemVerilog leading to a 40% reduction in bugs, demonstrated three state operations (Ideal, Setup, Enable), developed an APB protocol checker using SystemVerilog Assertions ensuring signal stability resulting in a 100% reduction in system failures, validated design’s functional correctness via simulation with identical data read and written to specific memory locations. Show less

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  Renesas Electronics

  Oct 2024 - now

  Technical Product Marketing Specialist