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Mrudula S

Mrudula S

Design and Verification Using Verilog

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location of Mrudula SBengaluru, Karnataka, India

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  • Timeline

  • About me

    Working as Senior Software Engineer.Autosar integrator and developer. Diagnostic (DCM and DEM), Communication stack ( CAN frame, LIN),BSW,RTE.

  • Education

    • Narayana Junior College - India

      2014 - 2017
      12th grade PCMB

    • RNS Institute of Technology - India

      2017 - 2021
      Bachelor of Engineering Electronics & Communication Engineering

  • Experience

    • Entuple Technologies Pvt. Ltd.

      Jul 2020 - Aug 2020
      Design and Verification Using Verilog

      I have completed 4 weeks internship in design and verification using Verilog. I was exposed to the Cadence tool for the digital design and the ASIC design flow.

    • Bosch

      Sept 2021 - Jan 2024
      Associate Software Engineer

      SW project developer for passenger cars (PC/LD)along with BRS projecs. Responsible for SW development(CAN frame,UDS), integration and testing.

    • Bosch Global Software Technologies

      Jan 2024 - now
      Senior Software Engineering

  • Licenses & Certifications

    • Hardware Description Languages for FPGA Design

      Coursera
      Jul 2020

    • ASIC Synthesis and Static timing Analysis (STA)

      Excel VLSI Technologies
      Apr 2020