Sunil Kumar Behera

Experience

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  Scaledge Technology

  Jul 2019 - Jul 2022

  Verification Engineer

  f/k/a PerfectVIPsIOMMU & IOTLB of PCIe Subsystem:• Developed the test plan for IOMMU.• Developed UVM environment to verify IOMMU.• Developed Page Table model for stimulus generation.• Developed IOTLB reference model to verify RTL.• Developed multiple agents.• Developed Scoreboard and checkers.• Developed Functional Coverage.• Performed regression setup and report generation.• Resolved issues regarding IOMMU.AXI4 back-to-back VIP:• Developed the test plan, assertion plan• Developed the UVM environment for verification of AXI4 Multi-Master & Multi-Slave• Developed the slave agent, driver, monitor, sequence, sequencer• Developed the interconnect for keeping track of the transaction of the component• Developed slave agent of interconnect• Worked on default slave agent• Worked on configuration class of AXI VIP• Developed assertion properties• Developed different operating states transitions and burst transfer for in AXI4 protocol• Developed SLVERR, DECERR and created testcases for the same• Developed scoreboard for AXI interconnect component• Worked on the master monitor Show less

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  Intel Corporation

  Aug 2022 - now

  SoC Design Verification Engineer

  Experienced SoC Design Verification Engineer with a focus on validation, specifically working on the Ethernet SoC (Granite Rapids D - 7nm) and involved in the emulation debug process for reset, FW & BIOS execution, and traffic testcases.