Aryan Tavakkoli

Experience

• 

  Imperial College London

  Jan 2014 - May 2017

  Graduate Teaching Assistant

  Lab Demonstrations:- Logic and Digital Systems (1st year students)- High-Level Synthesis for Real-time Parallel Image Processing (1st year students)- System-on-Chip Embedded Design (MSc students)Tutorial Sessions:- Mathematics (1st year students)Marking:- Assignments: Mathematics (1st year sheets)- Progress Tests: Logic and Digital Systems (1st year sheets)

• 

  Imperial College London

  Dec 2017 - Nov 2018

  Research Assistant

  Real-time per-kernel slack measurement for OpenCL applications on FPGAs

• 

  AccelerComm Ltd

  Jul 2019 - now

  Architected, designed, modelled, optimised, and verified vector processing designs, for 5G applications.Architecture/design work- Architected vector processing designs using AMD AI Engines.- Simplified algorithmic specification for much simpler designs.- Designed and developed vector processing blocks in C++ (for AMD AI Engines).- Developed functional testbenches in C++.- Optimised design for throughput, meeting requirements.Modelling work- Developed golden-reference models of 5G designs C++.- Developed algorithmic models in Matlab.- Developed MEX libraries in C++.- Coded several MEX interfaces in C++. Show less Patented two works in soft demodulation (each registered in UK and US), co-authored with Prof. Rob Maunder. Developed several algorithms from 5G standards, wrote test plans, and coded several testbenches in Matlab, including constrained-random testing.Patent work- Patented two works in soft demodulation (co-authored with Prof. Rob Maunder).- Developed patents' underlying algorithms in Matlab.- Generated results tailored to the research questions.- Wrote several reports from the work.- Wrote first drafts of the patent applications.Algorithms work- Developed models in Matlab for functionalities of NR 5G standards documents.- Read through 5G standard documents to find answers for specific questions.- Wrote test plan documents for functional testing of hardware blocks.- Developed constrained-random-testing testbenches in Matlab, providing coverage according to 5G standards. Show less

  • System Architect

    Nov 2023 - now

  • Senior Algorithm Engineer

    Apr 2023 - Oct 2023

  • Algorithm Engineer

    Jan 2021 - Apr 2023

  • IC Design Engineer

    Jul 2019 - Dec 2020