PARTHASARATHY B M

Experience

• 

  All India Radio

  Jan 2017 - Feb 2017

  Internship Trainee
• 

  Indian Railways

  Aug 2018 - Sept 2018

  Internship Trainee
• 

  TrEST Research Park

  Sept 2021 - Sept 2022

  Intern
• 

  Maven Silicon

  Nov 2021 - Jun 2022

  Intern

  Combinational and Sequential circuit Design | FSM Modelling | Static and Dynamic Timing Analysis | Memories | Verilog

• 

  Tata Elxsi

  Sept 2022 - now

  Hardware in Loop Simulation of Motorcycle EV Powertrain for a American OEM.. Experienced in Unified Diagnostic Services (UDS) and adapt at managing Diagnostic Trouble Codes (DTCs), ensuring streamlined and efficient vehicle diagnostics and troubleshooting. . This involved both manual control techniques using CANoe and automated testing methodologies through vTestStudio. . Got the experience in managing the Vector HIL Bench setups including VTBox (Cards like VT 2516, VT2004), CANoe and vTestStudio. Hardware in Loop and Model in Loop Simulation for ADAS Parking Function for a German Tier 1 Supplier.. Create Test Scenarios using IPG Carmaker for MIL & HIL Validation.. Virtual Validation using IPG Carmaker.. Flashing ECU with binaries and Validation using IPG Xpack4 Roadbox HIL Bench

  • Senior Engineer

    Sept 2022 - now

  • Senior Engineer

    Feb 2023 - Jun 2023

  • Senior Engineer

    Sept 2022 - Feb 2023