Kig Ling Yeong

Experience

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  Intel Corporation

  Apr 2002 - Dec 2007

  Design Engineer

  - Backend team-lead focusing on floorplan, integration and RV. Responsibilities include flow development and investigation and development and compilation of requirements for these three areas.- Fullchip owner for implementation of Network Processors at 180nm, 130nm & 90nm. Responsibilities include fullchip partitioning, partition area estimates and pin assignment, inter-partition routing and timing closure, die size finalization, clock tree implementation, and fullchip FEV.

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  Synopsys

  Jan 2008 - Apr 2017

  Staff Applications Consultant

  - Started off as the sole account AC for the Intel Penang & Altera Penang account, and the local on-site tool specialist for Design Compiler & IC Compiler. Also on-site representative for PrimeTime-PX, Formality, PrimeRail & UPF - Expanded into the role of ICC2-DP regional product lead for Asia.- Established, grew and managed the implementation AC team in Penang supporting both Intel Penang & Altera Penang account.

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  Intel Corporation

  Apr 2017 - Sept 2022

  Senior Structural Design Manager

  - Manage the Mixed Signal Malaysia IP Physical Design team. Integrated and delivered multiple generation of Intel Proprietary Die-to-Die IP.- Grew the team to own and deliver next gen DDR/LPDDR derivatives for Intel's SOC.- Partnered multiple outsource vendors to deliver on other stable IPs including USB2

• 

  Rapid Silicon

  Sept 2022 - now

  Senior Director

  Managing a global team working on next generation eFPGA and ASIC hardening.