Experience

• 

  Masi lab (microelectronics architecture integrated systems)

  Dec 1995 - Oct 1996

  Hardware designer

  Architecture, Design and test of data and instructions caches for a RISC microprocessor (MIPS R3000)• Specifications, modeling, test, synthesis and validation of I&D caches• Build macro-cell using RISC processor core and the I&D caches for system design verification & integration• Build Testbench using on chip PIBUS (Peripheral Interconnect Bus) and memory cores

• 

  Texas instruments

  Apr 1997 - Jun 2012

  In charge of OMAP & Modem based platforms/SoCs system verification & validation • Manage team of 65+ engineers and developing multiple projects/platforms in parallel. • Drive technology development, innovation to increase quality, execution efficiency and reduce costs• Manage requirements & execution across teams, IP, SOC design, prototyping, boards, software & customers• Demonstrate & achieve SOC/System functionality, power and performance• Team development, talent, skills, hiring, training, resources planning & forecasts• Interface customers ODM/OEM, Motorola, Nokia, Samsung, NEC,… customers’ problems solving & support• Enablement and collaboration with customers’ product development teams, hardware & software • Deployed validation activities in Eastern Europe: setup team, laboratory, equipments/tools…• Setup & deployed an offshore design center- Published SOW, managed partners selection & deployment of the design center infrastructure- Built the offshore development team: hiring, training & ramp project execution Show less Lead of OMAP SOCs project development & teams across GEOs, France, Dallas & India (Bangalore & Pune)• Responsible for development plans, execution and progress tracking and reporting to project stakeholders. • Ramped development teams in Bangalore & Pune (contractors)• Defined the development strategy, methods, tools and development environments • Developed & deployed Specman based design verification approach increasing efficiency of SOCs integration• Interfaced & worked closely with mobile customers eg, Nokia, through production and volume ramp Show less System On chip design - Mobile Phones GSM & EDGE/GPRS• Detailed knowledge of DSP “C55xx” micro-architecture• In charge of DSP core modeling and system integration• In charge of system “IPs” modeling, SOC integration & verification: memories, instruction cache, DMA & on chip bus controller• Developed the project verification infrastructure, tools, environment & tests software C, ASM• Set up flow for silicon debug test patterns development based emulation & functional model – TDL patterns• Developed new and inovative modeling & test methodology using formal & synhronuous tools eg, Esterel… Show less

  • Platform/SOC Development Engineering Manager

    Feb 2006 - Jun 2012

  • Senior Project Lead

    Feb 2003 - Feb 2006

  • Project Lead

    Feb 2001 - Jan 2003

  • DSP & SOC Development Engineer

    Jan 2000 - Jan 2001

  • DSP & SOC Development Engineer

    Apr 1997 - Jan 2000
• 

  Intel corporation

  Jul 2012 - now

  In charge of wearables product/platform definition and development from concept (MRD) to production• Lead development of Augmented Reality (AR) Devices from concept to production ramp. • Developed fully integated hw/sw form factor smartwatches, enabling key customers’ products eg, TAG Heuer, Fossil, New Balance: http://www.intel.com/content/www/us/en/wearables/tag-heuer-connected-watch.html • Performed architecture analysis and evaluation of new technologies for mobile/full AR Head Mounted Display and connected smartwatch Show less In charge of Intel Atom Z35xx, Z34xx ePOP processors/platform development spanning pre-silicon to production. Lead platform/processors definition, specifications and execution (plans, hw/sw integration, validation). Enablement and support of internal and external customers, Intel, ASUS.• Ensured plans, content development & execution on emulation platform and N-1 previous generation silicon• Managed the project budget, forecasts and reducing the overall development costs. • Drive hardware platform requirements & development eg, boards, daughter cards, sockets, debug tools• Completed the execution and achieved Atom Z35xx processor/platform production ramp in 2Q (ASUS phone)Lead Intel Atom Z34xx ePOP (LPDDR3/eMMC) processor design from concept, integration to production• Drive platform requirements, packaging and execution (plan, software integration, silicon) Show less

  • Wearable Products, Engineering Manager

    Jun 2015 - now

  • Platform Team Lead, Project Manager

    Jul 2012 - Jun 2015