Experience

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  Chipglobe gmbh

  Feb 2019 - May 2019

  Intern

  Created verification environment for APB2UART in a team of two (System Verilog UVM)

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  Chipglobe gmbh

  Aug 2019 - Oct 2020

  Digital design verification engineer

  • Developing Memory model in System Verilog UVM using uvm_mem class as a parent class • IP verification of protocols: SENT, Flexray, PSI5, PSI5S, I2C (language Specman e, methodology eRM)• coverage-driven constrained-random verification environments, coverage closure writing verification plan, development and maintenance of verification environments, creating FSDB files for power analysis,…

• 

  Hdl design house

  Oct 2020 - Jun 2024

  Mixed-signal design verification engineer

  • writing Top level testcases (AMS and DMS) • verification environment maintenance • writing Verilog AMS and wreal models for various mixed signal circuits; writing functional tests in Cadence Maestro and x-state tests• coverage-driven constrained random verification environments

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  Capgemini

  Jun 2024 - now

  Electronics & semicon engineer - digital and ams verification, ams modeling