Mikko Lintonen

Mikko Lintonen

ASIC Designer/Trainee

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  • Timeline

  • About me

    Principal R&D Engineer

  • Education

    • University of Oulu

      2003 - 2007
      M.Sc Electronics
  • Experience

    • Nokia

      May 2006 - Sept 2006
      ASIC Designer/Trainee

      • analog IP verification simulations against VHDL-AMS models.• Analog design for SIM IF

    • Nokia

      Jan 2007 - Nov 2007
      ASIC Design Engineer

      • Specification, RTL design & synthesis for mixed signal IC internal bus interface • Analog design• Top level verification simulations in VHDL-AMS environment• IP specification for mixed signal ICs

    • STMicroelectronics

      Nov 2007 - Dec 2009
      Design engineer

      • Touch screen IP analog driver design & system verification simulations • RTL design, Synthesis and verification for complex PLL IP inside mixed signal IC• PLL VCO jitter simulations• Analog design and verification for ISO-UICC and USB-UICC interfaces • Top level verification simulations in VHDL-AMS and Fast spice environments

    • ST-Ericsson

      Jan 2010 - Aug 2013
      Senior Design Engineer

      • FE design leader for WPC QI Wireless charging macro cell in ST-Ericsson charger IC.• Technical marketing support in customer interface.• Analog design & integration for the WPC QI protocol wireless charger macro cell.• RTL design, synthesis and verification of WPC QI protocol wireless charger macro cell.• I2C control interface integration to the wireless charger macro cell.• Wireless charger FPGA implementation and HW design support for test boards.• WPC QI standard wireless charger IC compliance testing in laboratory environment. Show less

    • Ericsson

      Aug 2013 - Dec 2014
      Technical project leader / Senior design engineer

      • Technical project lead for Ericsson next generation modem power management IC • Responsible on the IC performance and quality from specification to measurements• IP integration to IC Top level, both digital and analogue• IC architecture work to guarantee state of the art power consumption for Ericsson modem• IC clock management design, reference & bias management design• IC and IP testability design for silicon testing and customer testing• Support PCB design to minimize PCB area and guarantee performance• Verification leader for Ericsson modem mixed signal IC• Analog design & jitter analysis for programmable clock IOs• Analog design for accurate buck reference• Analog IP simulation script development for IP characterization Show less

    • Nordic Semiconductor

      Jan 2015 - now

      Analog and RF design lead for Nordic semiconductor long range radio RF & Analog design engineer

      • Principal R&D Engineer

        May 2024 - now
      • R&D Engineer

        Jan 2015 - Jun 2024
      • Senior R&D Engineer

        Jan 2015 - Jun 2024
  • Licenses & Certifications

    • Doulos Class-Based SystemVerilog Verification

      Doulos
    • Introduction to SystemVerilog

      Doulos
    • SystemVerilog Assertions

      Doulos