Surendra Pal Singh

Experience

• 

  Hindustan Aeronautics Limited

  Jun 2009 - Jul 2009

  Summer Intern

  During my internship at HAL, I got to know about:• Divisions and core business of HAL.• Products and Services offering of HAL.• Aircraft basics.

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  Ericsson

  Jun 2010 - Aug 2010

  Summer Internship

  At Ericsson, I got the opportunity to learn:• GSM Evolution/Generations of Mobile Communication.• GSM/GPRS architecture including functions of indivdual components like Base Transreceiver system, Base Station Controller, Transcoder Controller, Mobile Switching Centre.• Cell Planning.Besides above I got to work on Fault Management Layer of Network Management System. At the fault management level, network problems are found and corrected. Potential future problems are identified and steps are taken to prevent them from occurring or recurring. With fault management, the network stays operational, and downtime is minimized. Show less

• 

  Adobe

  Jul 2011 - Jun 2018

  Software Engineer

  At Adobe, I am involved with design, development and improvement for Adobe Photoshop Elements Organizer. It is a C++/Qt based media organizing application. Following is summary of work done on various releases of Photoshop Elements Organizer.Photoshop Elements Organizer 2018:• Search Revamp• Done UI reskinning of some visually outdated workflows in application.• Got CC India Promising Innovator 2016 and CC India Ideator 2016 award for prototyping and presenting Image Curation technology at Creative Cloud Innovation Month 2016.Photoshop Elements Organizer 15:• Gesture Support (Pinch and zoom, swipe and rotate).• Synchronize catalog.Photoshop Elements Organizer 14:• Place Caching:.• Showing dates in European Date format (YYYY/MM/DD).Photoshop Elements Organizer 13:• Alphabetical Sorting.• Advanced Search.• Looked the whole automation effort for Elements Organizer.Adobe Revel Client on Android:• Developed features from scratch, bug fixing.• Got Special Contribution Award for integrating Omniture library.ElementsCX: It is a web portal which shows the health of the product. I am involved in end to end design, development, testing, periodic data update, maintenance of Elements internal web portal comprising of user statistics, internal reports and development statistics in the form of dynamic tables, graphs etc. using WAMP stack and JavaScript libraries.Android Application - Citizen Connect:Bitbucket URL: https://bitbucket.org/surendra14/androidprogramming Show less

• 

  Synopsys Inc

  Jun 2018 - now

  I am responsible for design, development, optimization and debugging of Fusion Compiler’s Power Analysis segment. My core responsibilities include participating/leading design and architecture reviews, designing new features/flows, performance optimizations and debugging complex, high priority issues by our customers (including but not limited to Facebook, Apple, Samsung, Microsoft, Intel, AMD and MediaTek etc.).Also, I am actively involved in recruiting and mentoring Engineers for their growth and to build a high performing team.Fusion Compiler (FC) U-2022.12: Cycle/Time based power analysis by parsing FSDB file: • Collaborating with teams across different continents and influencing architectural decisions using technical and functional expertise. • Using NPI API’s, I am responsible for end-end design and development starting from reading FSDB file, getting value changes for an object and using these value changes for propagation. • Key challenge was to design a memory and runtime efficient engine as uncompressed FSDB files are huge in size.Fusion Compiler T-2022.03:• Saif_map block support: Incorporated observer design pattern to catch notification for commit_block and craft out saif_map for newly committed block from original saif_map.• Run time optimizations (eg. optimized runtime for '-saif_file' option by >65% (from 10 hours to 3.5 hours).Fusion Compiler S-2021.06:• Improving power accuracy by preserving activities on hierarchical ports: Pitched the idea to preserve activities on hier ports during optimizations. Designed and implemented full flow independently and within timelines. Received well by customers.• Building a robust saif map solution: Several notable enhancements include identifying third party netlist changes (MediaTek), identifying the stage of 'saif_map -start' (Google), adding fallbacks for PTPX mappings (Samsung), smart algorithm to detect the best RTL mapping (Microsoft). Show less Fusion Compiler R-2020.09:• Activity preservation in FC and PrimePower: Implemented activity observer support (based on observer design pattern) across modules for this. Debugging such issues required examining very large log files (80-100 GB plain text file) to locate point of activity loss. Eg. incorporating inhTermMap to give correct notification for polarity change (Qualcomm, AMD).Fusion Compiler Q-2019.12:• Enhancing saif map flow: One of the highest severities and highly visible feature tracked by many customers. Some prominent enhancement are removing elaborated objects from saif_map tracking; adding new options like -essential, -status, -debug (Samsung SARC), removing duplicate entries from both gate and rtl side, top level ports being inverted, enhancing/adding Inversion push functionality (ARM), enabling direction awareness in support in saif map.Fusion Compiler P-2019.03:• Designing DC map parser: Parse mapping file provided by Design Compiler (DC) and append this information to existing saif map information already available in FC. • Ownership Coverity issues and memory leak/corruption issues (investigated using Valgrind & Intel Inspector). Show less

  • Senior R&D Engineer II

    Dec 2020 - now

  • Senior R&D Engineer I

    Jun 2018 - Dec 2020