Mladen Knezic

Mladen Knezic

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  • Timeline

  • About me

    Associate Professor at University of Banja Luka | Embedded Systems Engineer

  • Education

    • Faculty of Electrical Engineering, University of Banja Luka

      2010 - 2017
      Doctor of Philosophy - PhD Electrical Engineering

      Research objective of doctoral dissertation entitled "Optimization of response time of industrial communication networks" was theoretical and experimental analysis of industrial communication systems with highest performance in terms of achievable communication cycle and the level of synchronization. Main contributions of the dissertation are:- review of the state-of-the-art in the research topic- development of theoretical and simulation models for considered industrial communication… Show more Research objective of doctoral dissertation entitled "Optimization of response time of industrial communication networks" was theoretical and experimental analysis of industrial communication systems with highest performance in terms of achievable communication cycle and the level of synchronization. Main contributions of the dissertation are:- review of the state-of-the-art in the research topic- development of theoretical and simulation models for considered industrial communication networks aimed at evaluating their performance metrics- new algorithms and methods for optimization of response time of the industrial communication networks- software for configuration of the industrial communication networks.The thesis was supervised by Prof. Branko Dokic. Full text (in Serbian) can be accessed on https://bit.ly/2zgDo6Q. Show less

    • Faculty of Electrical Engineering, University of Banja Luka

      2006 - 2010
      M.Sc. Electrical Engineering

      The main objective of the master thesis entitled "Contribution to the performance analysis of the EtherCAT system based on communication cycle time" was to develop a theoretical model for analysis of the EtherCAT industrial Ethernet based protocol in terms of achievable minimum communication cycle time. Main results of the thesis include:- theoretical models of the EtherCAT components for different configurations and network topologiesMATLAB simulation models which corresponds to the… Show more The main objective of the master thesis entitled "Contribution to the performance analysis of the EtherCAT system based on communication cycle time" was to develop a theoretical model for analysis of the EtherCAT industrial Ethernet based protocol in terms of achievable minimum communication cycle time. Main results of the thesis include:- theoretical models of the EtherCAT components for different configurations and network topologiesMATLAB simulation models which corresponds to the developed theoretical model- experimental characterization of the timing parameters of the developed models.The thesis was supervised by Prof. Branko Dokic. Full text (in Serbian) can be accessed on https://bit.ly/2DPVjFh. Show less

    • Faculty of Electrical Engineering, University of Banja Luka

      2000 - 2005
      B.Sc. Electrical Engineering

      The thesis entitled "Application of VHDL and FPGA technologies in an example of Software Defined Radio components design" presents an overview of the Software Defined Radio (SDR) concept and implementation of one of its components, namely Digital Down Converter (DDC) targeting an FPGA platform using VHDL hardware description language. More specifically, the implementation covers steps in designing the following functional blocks of the DDC: local numerically controlled oscillator (NCO), digital… Show more The thesis entitled "Application of VHDL and FPGA technologies in an example of Software Defined Radio components design" presents an overview of the Software Defined Radio (SDR) concept and implementation of one of its components, namely Digital Down Converter (DDC) targeting an FPGA platform using VHDL hardware description language. More specifically, the implementation covers steps in designing the following functional blocks of the DDC: local numerically controlled oscillator (NCO), digital mixer, Comb Integrator Cascade (CIC) filter and different types of Finite Impulse Response (FIR) filters (namely, CFIR and PFIR) specific to the SDR. Functionality of the designed DDC was simulated and verified using OrCAD software design suite.The thesis was supervised by Prof. Zlatko Bundalo. Full text (in Serbian) can be accessed on https://bit.ly/2AcJaGt. Show less

  • Experience

    • Faculty of Electrical Engineering, University of Banja Luka

      Feb 2006 - now

      - teaching activities (lab and oral exercises) in the following subjects: basic electronics (analog and digital), digital systems design based on FPGAs using VHDL language, industrial communication networks, design of systems based on microprocessors and microcontrollers- conducting a research related to the optimization of Real-Time Ethernet industrial communication systems (EtherCAT, Ethernet Powerlink, Profinet)- writing proposals for research projects- participating in research projects Show less

      • Associate Professor

        Feb 2023 - now
      • Assistant Professor

        Mar 2018 - Jan 2023
      • Senior Research and Teaching Assistant

        Feb 2010 - Feb 2018
      • Research and Teaching Assistant

        Feb 2006 - Jan 2010
    • University of Greenwich

      Feb 2013 - Feb 2013
      Visiting Researcher

      Study visit within project of interregional network of competence centres and regional nodes in the fields of industrial data communication and embedded systems (i-MOCCA) under supervision of Prof. Predrag Rapajic. Main activities and responsibilities include:- receiving a training about the PROFIBUS/PROFINET technologies- transferring the knowledge and experience about other Real-Time Ethernet technologies (EtherCAT and Ethernet Powerlink) to the members of the hosting research group- preparing a draft proposal for joint application for funds within the TEMPUS programme Show less

    • University of the Balearic Islands

      Apr 2014 - Jun 2014
      Visiting Researcher

      Conducting a research related to the fault-tolerance mechanisms (as a part of project FT4FTT: Fault Tolerance mechanisms for adaptive distributed embedded systems based on FTT-Ethernet) within academic mobility program of the Euroweb project under supervision of Prof. Julian Proenza. Main responsibilities include:- development of an FTT-SE simulation model on top of the INET framework for the OMNeT++ discrete event simulator- simulating different fault-injection scenarios aimed at verifying the developed fault-tolerance mechanisms- writing a conference paper reporting the obtained results Show less

    • Electronics Journal

      Jan 2018 - now
      Editor In Chief
  • Licenses & Certifications