Experience

• 

  Nec

  May 1991 - Aug 1995

  Researcher

  Core member of the team that defined the overall pipeline of the NEC's vector supercomputer. Later concentrated on the development of processor and ASIC for caches.

• 

  Hal computers (fujitsu)

  Sept 1995 - Dec 1996

  Manager

  Manager for the memory management unit of the SPARC compatible processor. Responsible for architecture, logic and timing.

• 

  Sandcraft

  Jan 1996 - Jan 1997

  Principal engineer

  Defined the architecture of the front-end of MIPS compatible processor, sold as 54XX series by NEC. Wrote verilog code for the front end of the machine (instruction cache, exception handling, branch logic, program counter logic), did floorplanning, performed static timing analysis, helped debug the tests.Was awarded patent #6055606 related to cache design of the chip.

• 

  Intel

  Jan 1997 - Jan 2001

  Senior staff engineer

  Worked on multithreading and on-chip multiprocessing technology for IA64 processors. Analyzed different multi-threading techniques, tradeoffs between the number of threads per core and the number of cores in terms of performance, area and ease of implementation. Defined the microarchitecture of the memory sub-system. Wrote iHDL code for memory management unit. Worked on novel power reduction techniques (patent #6564328) that had significant impact.Previously, helped the Itanium (IA64) processor in such diverse areas as microarchitecture of caches and load store units, fixing the layout issues, debugging tests, timing analysis. Worked on the architecture and implementation of multithreaded microengines of Intel's IXP series of network processors. The architecture consists of an ARM core and multithreaded microengines. This included defining the pipeline, interaction with other processors and components on the chip; wrote the verilog code. Show less

• 

  Procket networks

  Mar 2001 - Apr 2003

  Member technical staff

  Wrote code to generate and analyze traffic for performance analysis of internet routers using ixia packet generator. Verified portions of the network processing unit. Performed chip and system silicon bringup and helped in resolving system issues.

• 

  Sun microsystems

  Dec 2003 - Mar 2006

  Senior staff engineer

  Developed the multi-threaded, multi-processing modeling and verification environment for SUN’s next generation SPARC microprocessor. Wrote code in open-vera and verilog to verify the correctness of memory ordering and cache coherence for a large pool of hardware threads. Found several issues early in the design phase that would have caused low performance due to blocking, and correctness issues like deadlocks and livelocks. Wrote reference model for memory sub-system. Provided technical leadership to engineers and inputs to the management. Worked with cross-functional teams to have their tools ported on this environment. Developed testplans for verifying multicore memory sub-system. Analyzed algorithms related to DARPA related project for supercomputing. Show less

• 

  Redback networks

  Mar 2006 - Oct 2006

  Engineering manager

  Worked on the architecture of the next generation of network processor optimized for edge routing, VOIP and IPTV applications. Performed detailed analysis of the classification and flow processing that forms the frontend of the chip. Worked with software engineers and product management to get customer requirements and partition work into hardware and software components. Helped the current product development in terms of performance analysis and also to gather inputs for the next product. Isolated a number of issues related to memory bandwidth, on-chip interconnection network, TCAM lookup etc. Show less

• 

  Sun microsystems

  Oct 2006 - May 2007

  Senior staff engineer

  Developed the multi-threaded, multi-processing modeling and verification environment for SUN’s next generation SPARC microprocessor. Wrote code in open-vera and verilog to verify the correctness of memory ordering and cache coherence for a large pool of hardware threads. Found several issues early in the design phase that would have caused low performance due to blocking, and correctness issues like deadlocks and livelocks. Wrote reference model for memory sub-system. Provided technical leadership to engineers and inputs to the management. Worked with cross-functional teams to have their tools ported on this environment. Developed testplans for verifying multicore memory sub-system. Show less

• 

  Insilica

  Jun 2007 - Aug 2008

  Senior architect

  Participated in the successful tapeout of 2 ASICs related to cellular phones. Wrote the specifications for a part of one of the ASICs that was instrumental in the design win. Wrote the environment and model for a camera sensor for industry standard interface.

• 

  Arm

  Mar 2009 - Jun 2009

  Principal engineer

  Defined the microarchitecture for an ARM derivative processor to be used for automotive applications. Worked on redundancy at the core level and floorplan of the new processor. Also, defined the microarchitecture of an MMU that implements virtualization.

• 

  Applied micro circuits

  Sept 2010 - Feb 2017

  Senior manager

  Part of the team that verified the processor complex of 64b ARMv8 microprocessor.It consists of 8 CPU cores, level 3 cache, I/O bridge and memory controller. Verified RoCE (Remote DMA over Converged Ethernet), that allows a large number of independent processor nodes to communicate with low latency in a data center environment. Verified store buffer, bridge and domain protection for PowerPC. Performed pre-silicon and post-silicon performance analysis. Built a team of engineers. Worked on power aware verification of the CPU. Show less

• 

  Xilinx

  Mar 2017 - Apr 2020

  Design engineering manager 2

  Responsible for verification of AI Engine in Versal series of devices. It consists of a VLIW multiprocessor that communicates with the FPGA fabric and DDR. Applications include wireless and machine learning. Worked on it from start to end. The design is functional in silicon. Previously, responsible for CCIX (Cache Coherent Interconnect) verification that allows accelerators to be a part of cache coherence domain.

• 

  Perfectvips

  Jun 2020 - May 2021

  Director of engineering
• 

  Ceremorphic, inc.

  May 2021 - Nov 2021

  Director of engineering
• 

  Scaledge technology

  Dec 2021 - now

  Vice president of engineering