Experience

• 

  Intel corporation

  Jun 2010 - Jun 2022

  Responsible to overlook the path finding and execution activity for logic section of Optane memory division of Intel's NSG (Nand Solutions group).Responsibility involves but not limited to:1. Representing logic section to project management level staff meeting to update with current status, road blocks, spec level impact/updates, cross sectional communications etc. 2. Representing logic section in Spec sync up meetings where we discuss new feature requests from customer and/or Design teams to see the impact of the feature, cost assessment and negotiating approval and schedule impacts based on cost assessment data for particular feature. 3. Regular sync up with 4 logic pillars design, validation, back-end and standard cells. Collecting the status of where each pillar stands every week, understanding the technical and schedule related challenges and helping the team removing any road blocks for the team ensuring smooth execution.4. Heavily involved in cross-sectional communications to make sure proper technical information flow between sections and dependencies are resolved. 5. Responsible to define periodic milestones till DBR (data base ready - tape in) and regular tracking of each tasks per pillar to ensure progress by achieving all these milestones along the way to Project completion. 6. Responsible for development of multiple unit level test plan and full-chip level test plan, functional coverage development. Show less Fullchip validation:I owned fulchip validation focusing on logic controller block for Intel's Optane memory. Involved in developing verification plan, functional coverage, sequences to achieve functional coverage. UVM component development ex. Driver, Monitor, Scoreboard and Models which models the behavioral code to validate the design. Unit level validation:I was responsible for validation of data generation and comparator block heavily used to test functionality of array read/write and special modes. Sole owner for the validation environment and developer of UVM components to validate the design block. Show less

  • Technical Lead

    Aug 2019 - Jun 2022

  • Senior Component Design Engineer

    May 2017 - Aug 2019

  • Graphics hardware engineer

    Aug 2011 - May 2017

  • Component Design Engineer

    Jun 2010 - Jul 2011
• 

  Amd

  Jun 2022 - Jan 2024

  Smts silicon design engineer (verification)

  Technical Lead for Interconnect protocol IP (UCIE)Responsible for -Understanding the SPEC requirement and communicating with architects and designers. Detailed Planning and creation of the VIP development task list. Developing the architecture of top level layered VIP for UCIE.Leading the team for development of passive and active VIP components with UVMF for each layer.. Defining the architecture for inter layer communication. Providing technical guidance to junior teammates in resolving any technical issues related to layer level architecture and interlayer communication. .Driving the execution of VIP development according to the created tasklist aligning with project milestones. Representing as verification leader in project staff meetings and providing status as well as technical updates. Schedule risk assessment and planning to mitigate the risk by regular progress tracking and efficient resource management. Hands on technical ownership: Detailed layer level architecture for a layer as well as skeleton generation coding using UVMF. Complete ownership of Functional coverage plan as well as coverage coding. Driving coverage analysis and completion for the tapeout milestone for another AMD’s in-house die to die interconnect protocol. Show less

• 

  Broadcom

  Feb 2024 - now

  R&d engineer ic design (verification)

  Broadcom HBM PHY Verification - responsible for :- IP Verif: Verifying IEEE 1500 interface protocol (JDEC spec) for HBM. - Block Verif: Verifying embedded memory testing block