Experience

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  Face prep

  Jul 2021 - Aug 2021

  C++ programming mentor

  Technical Intern at faceprep. Taught C++, data structure and algorithms to students from colleges including VIT, SRM, SASTRA, PSGCAS and Velalar

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  Wipro

  Oct 2021 - now

  working as a contract STA engineer at NXP semiconductor, Bangalore. Handling SOC level STA for an IMX series chip. Updated chip level atspeed constraints, performed soc level pt run with 216 scenario's and generated reports for all violations mix wise. completed timing closure of 3 mixes in the NXP semiconductor's I. MX_95 chip. Experienced in solving Max transition, Max capacitance, setup, hold, mpw violations and perform PT eco to stabilize these violations in a block. Received appreciation as I closed timing for my mix firstly than all other mixes. performed ECO to fix all violations by inserting 1000+ buffers & sizing 1000+ cells. worked with NXP semiconductor in the static timing analysis of a mix. I was responsible for analyzing timing and solving issues (setup violations, hold violations, loops, timing constraint modifications, tran and cap violations, etc.) after getting confirmation from FE and DFT Teams in China and Europe. Learned about the physical design flow from synth to signoff.

  • STA Engineer

    Oct 2023 - now

  • VLSI STA Project Engineer

    Oct 2022 - Sept 2023

  • VLSI Physical Design Engineer

    Oct 2021 - Oct 2022