Tiến Anh Nguyễn

Tiến Anh Nguyễn

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location of Tiến Anh NguyễnHo Chi Minh City, Vietnam

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  • Timeline

  • About me

    Senior Design Verification Manager

  • Education

    • University of Technical and Education Ho Chi Minh

      2005 - 2010
      Bachelor of Engineering (B.E.) Electrical and Electronics Engineering

      Activities and Societies: Donate blood

  • Experience

    • Renesas Design Vietnam Co., Ltd.

      Mar 2010 - Sept 2015
      • Senior Hardware Engineer

        Mar 2013 - Sept 2015
      • Hardware Engineer

        Mar 2010 - Mar 2013
    • FPT Software

      Aug 2015 - Jun 2021

      - Review, direct and follow-up member’s objectives, assess member’s performance, and distribute appropriate bonus for each member. - Review, consult and confirm all project plans and project processes in the groups. - Design and apply programs to retain human resources, keep the Turn-Over Rate as low as possible.- Regular review and control resource allocation to keep high efficiency effort in the group. - Present group’s capacity and discuss with potential customer to expand business.- Conduct interviews of new candidates for hardware design and functional verification positions. Perform basic verification training for freshers and soft skill training for group’s members. Show less

      • HCM LSI Business Leader

        May 2020 - Jun 2021
      • Technical Project Manager

        Feb 2017 - Jun 2021
      • Senior Verification Engineer

        Aug 2015 - Jan 2017
    • Bosch Global Software Technologies

      Jul 2021 - Feb 2022
      Project Manager

      - Manage projects belonging to automotive domain (Driving Assistance): SW application on Radar ECU.- Work with COEM (China) customer & JOEM (Japan) customer.- Manage: Project scope, timeline, quality & quality gates, process, budget, ...- Collaborate with engineers, project managers on multiple sites from other countries: India, Japan, China by conducting regular project meetings.

    • DreamBig Semiconductor Inc.

      Mar 2022 - Nov 2024
      Design Verification Manager

      - Propose verification plan and test plan then review with Architectures and Designers for Packet Buffer Block level and full-chip level.- Build up UVM environment skeleton from scratch for unit-level verification then re-use it for full-chip level environment.- Collaborate with Pakistan verification team to build-up full-chip environment: Porting block-level components, develop end-to-end scoreboards, UVM base test, UVM register model.- Propose test plan for peripherals: UART, PLL, sub-modules inside Packet Buffer; review test plan for I2C, I3C.- Create and execute random test, debug and report bugs for design team in Vietnam and Pakistan.- Review test plan, UVM development, test cases for team members.- Conduct Sprint meeting to define 2-week plans, and follow-up, collect status of Vietnam Verification team.- Discuss and report overall status of verification project in regular multiple-site (US & Pakistan) meetings- Do strict recruitment, make verification training and conduct the training for freshers. Show less

    • Marvell Technology

      Oct 2024 - now
      Senior Design Verification Manager
  • Licenses & Certifications

    • Project Management Professional (PMP)®

      Project Management Institute
      Dec 2018
      View certificate certificate
    • PMI Agile Certified Practitioner (PMI-ACP)

      Project Management Institute
      Nov 2019
      View certificate certificate