
Timeline
About me
Chercheur Postdoctoral in Embedded System Engineering, SnT, Interdisciplinary Centre for Security, Reliability and Trust
Education

Université côte d'azur
2016 - 2020Doctor of philosophy - phd software and system engineering with honors
Université de nice-sophia antipolis
2009 - 2014Master's degree fundamental computer science, software engineering with honors, major
Experience

Visteon corporation
Sept 2013 - May 2019Research Engineer in Graphic Embedded Systems, R&D
Jan 2017 - May 2019Embedded Graphic Software Engineer, R&D
Sept 2014 - Jan 2017Apprentice in Graphic Embedded Software Engineering
Sept 2013 - Aug 2014

I3s/cnrs
Jan 2016 - Dec 2020Phd candidate in embedded graphic system engineering.webp)
Université nice sophia antipolis (membre d'université côte d'azur)
Sept 2016 - May 2018Part-time teacher in software engineering
Snt, interdisciplinary centre for security, reliability and trust
Sept 2020 - nowChercheur postdoctoral
Licenses & Certifications

Java se 7 programmer
OracleJul 2014
Toeic
Ets globalJan 2014
Honors & Awards
- Awarded to Sami LazregLauréat du Prix d'Exellence 2018 de l'Université Côte d'Azur Université Côte d'Azur Dez. 2018 http://univ-cotedazur.fr/events/prix-excellence/#collections
- Awarded to Sami LazregBest Paper Award for Major Contribution in Software Design and Development 33th ACM Symposium On Applied Computing Association for Computing Machinery (ACM) Apr. 2018 The paper entitled "Assessing the Functional Feasibility of Variability-Intensive Data-Flow oriented Systems" propose a new approach to verify, in early design phase, the feasibility of embedded systems implementations.Rather than enumerate and iteratively assess all system designs, the proposed framework reason on behavioral product line to assess, in an optimized manner, the whole design space in a single variability-aware model checking run.The experiments show that this approach… Mehr anzeigen The paper entitled "Assessing the Functional Feasibility of Variability-Intensive Data-Flow oriented Systems" propose a new approach to verify, in early design phase, the feasibility of embedded systems implementations.Rather than enumerate and iteratively assess all system designs, the proposed framework reason on behavioral product line to assess, in an optimized manner, the whole design space in a single variability-aware model checking run.The experiments show that this approach exploits behavioral commonalities between system designs to speed-up remarkably the verification process. Weniger anzeigen
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