Experience

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  Infineon technologies

  Dec 2009 - Apr 2018

  - Participation in the entire development cycle of catalog PMICs. Main activities included: specification analysis, design feasibility, concept validation, transistor-level circuit design, die-size estimation, layout support, block- and top-level verification, lab validation and qualification support.- Execution and debugging of Analog/Mixed Signal simulations at top level (using Spectre & AMS simulators).- Focus on low-power solutions, design for testability (DFT) and design for manufacturability (DFM).- Coordination, evaluation and utilization of package and PCB extractions for modelling of board parasitics.- Silicon debugging in lab including measurements automation and coordination of failure analysis activities.- Knowledge and experience in the following systems: DC/DC Buck converters (VIN=16V, VOUT=1.2V, IOUT=100A), DC/DC resonant LLC converters (VIN=100V, VOUT=20V, IOUT=10A) and Three-Phase Bridges for BLDC motor applications (VIN=85V, IOUT=10A).- IC design and verification of power management blocks using 130 nm HV CMOS and BCD processes. These include: * Generic blocks such as OPAs/OTAs (Class A and AB), comparators, UVLOs, oscillators, I/V references, bandgaps, voltage regulators, trimming circuitry. * Higher complexity circuits such as a negative charge pump (5mA output capability), a high current LDO (500mA output capability), an accurate temperature sensor (+/-2˚C), a very accurate auto-zeroed current sensor (+/-2%), a 7-bit SAR ADC (LSB=8 mV) and an accurate auto-zeroed voltage sensor (+/-2%) with high input voltage (85 V). Show less - Master Thesis development.- Investigation via Finite Elements Method of current sense accuracy for a sensing cell embedded in a DMOS power MOSFET. Identification of the factors of influence and proposal of corrective measures.- Development of an adequate front-end board for current sense measurements and execution of automated lab measurements using MATLAB Control Toolbox.- Design, analysis and simulation in Cadence environment of an auto-zeroed op-amp in 130 nm CMOS process for an integrated current sense application. Show less

  • Analog & Mixed Signal Designer

    Nov 2010 - Apr 2018

  • Intern

    Dec 2009 - Oct 2010
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  Texas instruments

  May 2018 - Sept 2024

  Analog & mixed signal designer

  - Participation in the entire development cycle of custom and catalog PMICs.- Focus on low-power and minimum area solutions, design for testability (DFT) and design for manufacturability (DFM).- Knowledge and experience in the following systems: Buck, Boost, Inverting Buck-Boost, and Non-Inverting Buck-Boost DC-DC converters. Current-Controlled and Hysteretic Topologies. Dual Phase and Three-Level Architectures.- IC design and verification of power management blocks using 130 nm BCD processes. Main circuits: current sense, gate drivers, LDO's, level-shifters, OP-AMPs, zero-cross and peak detector comparators.- Other key activities: * Design feasibility and proof of concept at circuit and at converter level. * Modelling of main blocks. * Efficiency estimation and loss contributors breakdown. * Strategies and optimization for best-in-class efficiency. * Effort estimation and schedule definition for the key activities and blocks. * Chip floorplan and area estimation. * Direct interaction with the customer. * Reliability analyses (electro migration, floating nodes, SOA). * Planning and follow-up of ESD reviews with experts. * Definition of DFT strategy with test engineers. * Lab debugging and support to validation engineers. Show less

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  Monolithic power systems, inc.

  Sept 2024 - now

  Analog & mixed signal designer