Experience

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  T.i.m.e. (triumphant institute of managment education)

  Jul 2016 - Dec 2017

  Senior lecturer

  Lecturer of GATE paper (Electronics and Communication Engineering)

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  National institute of technology nagaland

  Jan 2018 - Jun 2022

  Ph.d (senior research scholar)
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  Sandeepani- school of embedded system design

  Jun 2020 - Jul 2020

  Fpga design and verification intern

  Software : VIVADOHardware ZedBoard Zynq-7000 ARM/FPGA SoC Development BoardDetails: Hardware ModellingVerilog language Test benches WritingCoding For SynthesisFPGA Architecture -BasicComponents of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, ZynqFPGA Design Flow -Xilinx Vivado tool Flow, Reading Reports, and Implementing IP cores.Optimal FPGA Design -HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation OptionsStatic Timing Analysis -Global Timing Constraints, Achieving Timing Closure, Introduction to Reset techniques Show less

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  Sandeepani school of vlsi design

  Aug 2020 - Oct 2020

  Software : 1. DESIGN AND SIMULATION:-Tanner S-Edit, Tanner T-Spice, Tanner Waveform Viewer 2. RF Domain:-Tanner Eldo RF AMS/ELDO 3. LAYOUT:- Tanner L-Edit IC, Tanner EDA Place and Route 4. PHYSICAL VERFICATION:-Tanner Calibre OneDetails: Full custom design flow MOS switches and designTransistor model -full custom design VI Characteristics of MOS, Transmission Gates MOSFET Combinational and sequential logic Aspects of Physical Layout modelSPICE Generation, Analysis and Physical Verification Aspects Show less

  • Physical Design and Verification - RTL2GDSII

    Sept 2020 - Oct 2020

  • ASIC – Physical Design and Verification Intern

    Aug 2020 - Sept 2020
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  Sandeepani school of vlsi design

  Feb 2021 - Mar 2021

  Functional verification using systemverilog

  Software: Mentor graphics - Questasim,

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  Collins aerospace

  Nov 2021 - Jul 2022

  Associate engineer

  Description: Resolver to digital converter controller IP design– Duration: 6 months– Role:∗ RTL coding in VHDL of design module and its integration in Questasim.∗ Write VHDL test bench to test the implemented feature.∗ Micro-architecture and User-Guide template.∗ Modification design Specification.

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  Msdlab @ indian institute of science

  Aug 2022 - now

  Research
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  Indian institute of science (iisc)

  Aug 2022 - now

  Research assistant